1. Field of the Invention
The present invention relates to a net list producing device, and particularly to a net list producing device producing a net list with an interconnection parasitic element by hierarchical processing.
2. Description of the Background Art
Conventionally, methods of producing a net list with an interconnection parasitic element of a small data quantity for circuit simulation have been proposed.
For example, a method in Japanese Patent Laying-Open No. 2004-094402 employs delay model producing means 4 receiving a prelayout net list 1, an LPE net list 3 of a result of extracting layout parasitic elements, and an LPE information correlating property 2 correlating LPE net list 3 and prelayout net list 1 with each other, and producing a delay model file 5 from prelayout net list 1 and LPE net list 3 according to details of LPE information correlating property 2. This method also employs delay simulation net list producing means 6 (i.e., net list producing means for a delay simulation) producing a net list 7 for a delay simulation from delay model file 5 and prelayout net list 1.
However, the method of Japanese Patent Laying-Open No. 2004-094402 has not disclosed means for producing the LPE information correlating property forming an input. The pin name (physical terminal name) described in the LPE information is present in the LPE net list, but is not present in the prelayout net list, and it is impossible to produce the delay simulation net list (i.e., net list for a net simulation) for a whole memory from information of only logical terminal names described in the prelayout net list.
According to Japanese Patent Laying-Open No. 2004-094402, therefore, it is actually impossible to produce the net list with the interconnection parasitic element of a small data quantity.